1. Field of the Invention
The present invention relates to a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit capable of preserving data without a leakage current during a sleep mode using MTCMOS technology.
2. Discussion of Related Art
A latch circuit has one data input, one clock input, and one output. When the clock input is activated, input data is received and transferred to an output side, and when the clock input is deactivated, the data is preserved in a feedback circuit.
FIG. 1 is a circuit diagram of a conventional latch circuit using a single threshold voltage, FIG. 2 is a circuit diagram of a conventional clock signal generation circuit, and FIGS. 3A to 3C illustrate transistor equivalents of elements shown in FIG. 1.
Referring to FIGS. 1 to 3C, the latch circuit using a single threshold voltage includes a transmission gate 100 controlled by a clock signal CP and an inverted clock signal CPb, a NAND gate 110 outputting data D in response to a reset control signal RS, a first inverter 120 inverting the signal output from the NAND gate 110, and a feedback transmission gate 130.
The clock signal CP and the inverted clock signal CPb are generated by the clock signal generation circuit shown in FIG. 2. The clock signal generation circuit includes a second inverter 210 and a third inverter 220.
Therefore, when a clock control signal CLK in a high state is input, the inverted clock signal CPb in a low state is output by the second inverter 210, and the clock signal CP in the high state is output by the second inverter 210 and the third inverter 220. On the contrary, when the clock control signal CLK in a low state is input, the inverted clock signal CPb in a high state is output by the second inverter 210, and the clock signal CP in the low state is output by the second inverter 210 and the third inverter 220.
As illustrated in FIG. 3A, the transmission gate 100 consists of a p-channel metal oxide semiconductor (PMOS) transistor and n-channel metal oxide semiconductor (NMOS) transistor having a medium threshold voltage.
As illustrated in FIG. 3B, the NAND gate 110 consists of PMOS transistors and NMOS transistors having a medium threshold voltage.
As illustrated in FIG. 3C, the first, second and third inverters 120, 210 and 220 each consist of a PMOS transistor and NMOS transistor having a medium threshold voltage.
Operation of the latch circuit constructed as described above will be described below.
When the reset control signal RS is in a low state, the NAND gate 110 outputs the signal in a high state regardless of an input state of the data D, and an output Q is maintained in a low state by the first inverter 120.
On the contrary, when the reset control signal RS is in a high state and the clock control signal CLK is in a high state, the clock signal CP becomes the high state and the inverted clock signal CPb becomes the low state. Thus, the transmission gate 100 becomes an on state and the feedback transmission gate 130 becomes an off state.
Here, when the data D is in a high state, the output Q becomes a high state, and when the data D is in a low state, the output Q becomes a low state.
In addition, when the clock control signal CLK is in a low state, the transmission gate 100 becomes an off state and the feedback transmission gate 130 becomes an on state. Thus, the output Q is maintained in a state of previous data.
However, the conventional latch circuit using a single threshold voltage as described above has problems in achieving high performance and low power consumption due to a leakage current caused by scaled-down elements.